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Modules · Home · Downloads · FAQ · Feedback · Recommend Us · Web Links · Your Account Advertising Who's Online There are currently, 21 guest(s) and 2 member(s) that are online. You are Anonymous user. You can register for free by clicking here Login Nickname Password Security Code: Type Security Code Don't have an account yet? You can create one. As a registered user you have some advantages like theme manager, comments configuration and post comments with your name.    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Assertions on VHDL Variables          Verification Guild Forum Index -> Assertions View previous topic :: View next topic   Author Message bugfinder Senior Joined: Jan 12, 2004 Posts: 19 Posted: Tue Dec 21, 2004 9:11 am    Post subject: Assertions on VHDL Variables Can we write PSL/SVA assertions for properties on VHDL variables?(especially temporal ones). Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1045 Location: Los Angeles, CA Posted: Tue Dec 21, 2004 4:24 pm    Post subject: Quote: Can we write PSL/SVA assertions for properties on VHDL variables?(especially temporal ones). NO, you cannot in PSL because assertions are concurrent statements and cannot be written in VHDL processes,which may contain the variables. Outside teh context of a process, the local process variables are inaccessible. Yes you can in SystemVerilog Assertions because one can write assertions in always blocks. Also, SV allows the path to access objects within named blocks. Thus, concurrent assertions can also access local variables of named blocks. Ben Cohen _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 2nd Edition, 2010 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top srini Senior Joined: Jan 23, 2004 Posts: 408 Location: Bengaluru, India Posted: Tue Dec 21, 2004 9:39 pm    Post subject: vhdlcohen wrote: Yes you can in SystemVerilog Assertions because one can write assertions in always blocks. Also, SV allows the path to access objects within named blocks. Thus, concurrent assertions can also access local variables of named blocks. Ben Cohen Ben, The OP was more interested in VHDL variables and as such I don't see either PSL or SVA LRMs explicitly allowing this. PSL is clearly context unaware and hence won't be able to do this as it stands. SVA is capable, but in-lining is not defined in LRM, hence vendors need to agree on a pseudo-standard. However, I'm curious as to what the OP intends to check for. Temporal on Variables? Why can't he use a signal instead? For non-temporal ones, VHDL's assert should do the job. Bugfinder - can you please clarify? Thanks, Srini _________________ Srinivasan Venkataramanan Chief Technology Officer, CVC www.cvcblr.com A Pragmatic Approach to VMM Adoption SystemVerilog Assertions Handbook Using PSL/SUGAR 2nd Edition. Contributor: The functional verification of electronic systems Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1045 Location: Los Angeles, CA Posted: Tue Dec 21, 2004 10:02 pm    Post subject: Srini, You make a good point. I was really answering a side question about always block variables in SV being checked with SVA, which they can. But you are correct, the original post was on SVA checking VHDL variables, which, like PSL, it cannot. Sorry Bugfinder for the confusion, and thanks Srini for clarifying the issues. Ben Cohen _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 2nd Edition, 2010 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top srini Senior Joined: Jan 23, 2004 Posts: 408 Location: Bengaluru, India Posted: Wed Dec 22, 2004 3:09 am    Post subject: vhdlcohen wrote: Srini, You make a good point. I was really answering a side question about always block variables in SV being checked with SVA, which they can. Ben, I know you are aware of this, but just wanted to clarify - by "always block variable" we mean "local variables declared within always block" (BTW, in SV we can declare local vars even in unnamed blocks - unlike Vlog 2001 - wherein only named blocks had that). I think PSL won't be able to see them either. Quote: But you are correct, the original post was on SVA checking VHDL variables, which, like PSL, it cannot. Ben Cohen Well, SVA *can* - with some help/agreement from tool vendors as it is defined to be "context aware". But I will re-insist that using a specialized assertion language for this purpose sounds like an overkill to me - what happened to VHDL's in-built assert construct?? Thanks, Srini _________________ Srinivasan Venkataramanan Chief Technology Officer, CVC www.cvcblr.com A Pragmatic Approach to VMM Adoption SystemVerilog Assertions Handbook Using PSL/SUGAR 2nd Edition. Contributor: The functional verification of electronic systems Back to top cindy Industry Expert Joined: Aug 17, 2004 Posts: 298 Posted: Wed Dec 22, 2004 4:08 am    Post subject: bugfinder asked: Quote: Can we write PSL/SVA assertions for properties on VHDL variables?(especially temporal ones). to which ben answered: Quote: NO, you cannot in PSL because assertions are concurrent statements and cannot be written in VHDL processes,which may contain the variables. Outside teh context of a process, the local process variables are inaccessible. and srini added: Quote: PSL is clearly context unaware and hence won't be able to do this as it stands. these responses seem to be based on the assumption that the only way to access vhdl variables is from inside vhdl. but a psl assertion is written about the vhdl, not necessarily inside of it (and indeed, the psl lrm does not currently define embedding assertions within the code). as such, there is no reason that you cannot write a psl assertion about a vhdl variable. as i said on a previous thread, as far as the language is concerned, there are two issues: Quote: first, can you write a boolean expression containing a vhdl variable? (i don't know vhdl, but i assume that something like "a>b" would be boolean no matter the type of "a" and "b".) if the answer to this question is yes, then it is possible to write a psl assertion that refers to a vhdl variable. second, can your verification tool access the values of the vhdl variables (for instance, to display them in a waveform)? if the answer to this question is yes, then it is possible to implement support for such a psl assertion in the tool. whether or not tools support this is another matter. note that on the previous thread, ajeetha pointed out that modelsim allows vhdl variables to be viewed as a waveform. so in principal, modelsim could be enhanced to support psl properties about vhdl variables, if it does not already do so. cindy. Back to top srini Senior Joined: Jan 23, 2004 Posts: 408 Location: Bengaluru, India Posted: Wed Dec 22, 2004 5:43 am    Post subject: cindy wrote: these responses seem to be based on the assumption that the only way to access vhdl variables is from inside vhdl. Cindy, As per VHDL LRM, variables (except shared ones, leave it aside for now) are NOT accessible outside their prcoess scope - within the language. However as you mentioned, a tool may extend the capability - but then any code written that way will be non-portable. Quote: but a psl assertion is written about the vhdl, Very well said, and that's why I keep saying we don't need any fancy assertion language for the purpose OP asked for. Quote: not necessarily inside of it (and indeed, the psl lrm does not currently define embedding assertions within the code). as such, there is no reason that you cannot write a psl assertion about a vhdl variable. This is some what like a catch22 situation as I see it. Only from within a VHDL process we can access a variable, and PSL as it stands today can't be aware of the "place" where it is embedded - infact as you correctly pointed out, embedding is not in the LRM itself - though "psl" pragma is a pseudo-standard. Quote: second, can your verification tool access the values of the vhdl variables (for instance, to display them in a waveform)? But there is a significant difference in the two - a waveform viewer/format (remember NO VCD is in LRM for VHDL) for VHDL is properitary (I wonder what happened to the WAVES standard!!). Hence a tool is at its freedom to access/show every thing it likes as there is no question of inter-operability (unfortunately?). Whereas an assertion is more of a "specifcation/requirement" and hence by definition should be portable across implementations. I think that's one of the primary objectives of standardizing assertion languages at the first place. So I disagree that the comparison of PSL accessing a VHDL variable and viewing it in waveform are similar. Thanks, Srini P.S. Please note: I am not favoring one language over the other here, infact I would love to get back to the OP and ask him/her - why would he/she want to write an assertion in PSL/SVA on a VHDL Variable (and that too a temporal one). _________________ Srinivasan Venkataramanan Chief Technology Officer, CVC www.cvcblr.com A Pragmatic Approach to VMM Adoption SystemVerilog Assertions Handbook Using PSL/SUGAR 2nd Edition. Contributor: The functional verification of electronic systems Back to top cindy Industry Expert Joined: Aug 17, 2004 Posts: 298 Posted: Wed Dec 22, 2004 9:42 am    Post subject: srini, Quote: This is some what like a catch22 situation as I see it. Only from within a VHDL process we can access a variable, and PSL as it stands today can't be aware of the "place" where it is embedded - infact as you correctly pointed out, embedding is not in the LRM itself - though "psl" pragma is a pseudo-standard. but my point is that psl is not necessarily embedded at all! the way psl is defined in the lrm, and the way we use it at ibm, it stands apart from the vhdl. thus, the only parts of the vhdl lrm that affect psl are those that are explicitly pointed to by the psl lrm. and all the psl lrm says about vhdl is that in the vhdl flavor, ieee 1076-2002 syntax is used for boolean expressions (section 4.1.2.3 of the psl lrm), and that the vhdl flavor of the modeling layer is the synthesizable subset defined by ieee 1076.6-1999. thus, while i would agree that the modeling layer is affected by the restriction on the use of vhdl variables, i would not agree that the boolean layer is. cindy. Back to top Janick Site Admin Joined: Nov 29, 2003 Posts: 1317 Location: Ottawa, ON Canada Posted: Thu Dec 23, 2004 11:03 am    Post subject: srini wrote: I wonder what happened to the WAVES standard The WAVES standard was for defining waveforms and timesets on harware testers (i.e. stimulus and expected response following specific ege placements and sample windows), not as a database for waveform viewers. Back to top bugfinder Senior Joined: Jan 12, 2004 Posts: 19 Posted: Fri Dec 24, 2004 6:22 am    Post subject: VHDL Variables Thanks to everyone. Srini, We are following one RTL coding guidelines for several years to use variables instead of signals wherever possible to speed up the simulation. Yes we can use signals to do the same job. In this context I was curious how we can adapt PSL while still following our old RTL coding guidelines. Cindy, Thanks. Currently we are using a tool which converts PSL to VHDL and use it in testbench and the only type of variable we can currently look at would be signals as all the elements should be on entity ports or use some signal spying feature provided by the simulator. But this works only for signals as no spy feature is currently available for variables. Thanks. Back to top vhdlcohen Industry Expert Joined: Jan 05, 2004 Posts: 1045 Location: Los Angeles, CA Posted: Fri Dec 24, 2004 4:19 pm    Post subject: Quote: We are following one RTL coding guidelines for several years to use variables instead of signals wherever possible to speed up the simulation. Yes we can use signals to do the same job. In this context I was curious how we can adapt PSL while still following our old RTL coding guidelines. I would then suggest that for those variables that you need to associate a property with you make signal assignments of those variables onto signals, and use the signals in your PSL. As a general guideline, I prefer to use signals throughout, except when the data structire is too large (like large arrays). I occasionaly use variable as temporary computational variables. Thus, my guidelines are a bit different than yours. In the realm of things, and given that machines are much faster today, using signals that do not represent large data structures do not significantly slow down simulation. Ben Cohen _________________ Ben Cohen http://www.systemverilog.us/ * SystemVerilog Assertions Handbook, 2nd Edition, 2010 * A Pragmatic Approach to VMM Adoption * Using PSL/SUGAR ... 2nd Edition * Real Chip Design and Verification * Cmpt Design by Example * VHDL books Back to top Display posts from previous: All Posts1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year Oldest FirstNewest First         Verification Guild Forum Index -> Assertions All times are GMT - 5 Hours Page 1 of 1   Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  You can post new topics in this forum You can reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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